A simulation tool running on a computer is used to test a logic circuit design for an integrated circuit prior to manufacture of the integrated circuit. Logic signal waveforms generated in the simulation are recorded and later analysed by using a waveform display tool. A typical logic simulation of a circuit block of an Application Specific Integrated Circuit (ASIC) involves the use of one or more clocks running for an extended period of time. The clocks are normally of the order of tens to hundreds of Megahertz (MHz), and a simulation time is normally from several milliseconds to a second. Recording such high frequency signals results in a vast amount of recorded data. One common file format used to record all simulation logic waveforms is the industry standard Value Change Dump (VCD) format. The VCD format records separate transition data for each transition edge in the signal. However, the size of a VCD format file is often prohibitively large to be handled by the waveform display tool. File size problems include (i) a file being too large to be loaded; (ii) causing the waveform display tool to crash in use; and (iii) forcing the user to select only a small portion of the recorded waveforms to load, making it difficult to compare waveforms at different times in the recorded simulation.
Further problems relate to the displaying of recorded clock signals by the waveform display tool. Often, the frequencies of the clock signals are several orders of magnitude higher than most of the other signals in the simulation. When displaying waveforms over an extended period of time in a time-compressed window, a large number of clock signal transitions are displayed. The clock signals are compressed along a time-axis of the display window. Individual edges of a signal can only be distinguished in the display provided that that waveform detail does not exceed the resolution of the display apparatus. In many cases individual edges are not distinguishable. The speed at which the display tool can generate a display of the waveform depends largely on the number of waveform transitions that are displayed. Graphics vectors are drawn for each transition to show the waveform shape. Displaying the clock signals often occupies up to 75% of the display generation overhead. Such overhead is wasted if the time-axis compression is such that individual clock edges are not distinguishable in the generated display.